This invention relates to spread-spectrum communications, and more particularly to an architecture for implementing a bit matched filter requiring less silicon and consuming less power, as compared to existing designs.
A bit-matched filter normally is used for correlating an input signal with a reference signal. The term xe2x80x9cbit-matched filterxe2x80x9d, as used herein, is a matched filter matched to a particular chip-sequence signal, where the number of chips matched in the bit-matched filter equates to an information bit. The chip sequence is used for spreading the information bits at a spread-spectrum transmitter.
Correlating with the bit-matched filter is accomplished by multiplying a set of N samples of the input signal with the reference signal, then summing the product terms as follows:       S    ⁡          (      N      )        =            ∑              i        =        1            N        ⁢                            {                                    d              y                        ,            …            ⁢                          xe2x80x83                        ,                          d              1                        ,                          d              0                                }                i            *              R        i            
where N is the number of taps of the bit matched filter, S(N) is the sum of the product terms, d{y, . . . , 0} are the data samples with (y+1) bit resolution, and Ri reference signal samples. N and y are positive integer numbers.
There are a number of different architectures for implementing a bit-matched filter disclosed in the prior art. One such method is tabulated in table 1, for comparing with the bit-matched filter of the instant invention.
For this example, the prior art bit-matched filter is assumed to have N=512 samples, with eight bits per sample. The prior art bit-matched filter requires eight banks of shift registers of 512 registers per bank, for a total of 4096 registers. Also 4096 exclusive-OR (XOR) gates are required for implementing one bit multiplier function.
For the adder function, the requirements are: 256 eight bit adders, 128 nine bit adders, 64 ten bit adders, 32 eleven bit adders, 16 twelve bit adders, 8 thirteen bit adders, 4 fourteen bit adders, 2 fifteen bit adders and 1 sixteen bit adders.
With some technologies, data can not be propagated through 11 levels of adder blocks and meet the setup time at the next functional block, pipeline register banks are normally required.
A general object of the invention is a matched filter having a low silicon and a low power requirement. Another object of the invention is a bit-matched filter requiring fewer exclusive-OR gates, compared to the prior art bit-matched filter.
According to the present invention, as embodied and broadly described herein, a spread-spectrum-matched filter is provided for use as part of a spread-spectrum receiver on a received-spread-spectrum signal. The received-spread-spectrum signal has a plurality of information bits, and is generated at a spread-spectrum spectrum transmitter by spread-spectrum processing each information bit with a chip-sequence signal. The present invention for the spread-spectrum matched filter is taught, by way of example, by breaking a filter length into two halves of length N/2 each where N is the number of taps on the matched filter. The spread-spectrum matched filter may have the filter length broken into more sections, e.g., four sections of length N/4, eight sections of length N/8, etc., by extending the concepts taught herein for two sections.
The spread-spectrum-matched filter can be used as part of a spread-spectrum receiver, for receiving a spread-spectrum signal. A received-spread-spectrum signal, as used herein, is a spread-spectrum signal arriving at the input of the spread-spectrum receiver. Timing for the present invention may be triggered from a header as part of a packet or from a pilot-spread-spectrum channel. For the case of the header, the received-spread-spectrum signal is assumed to include a plurality of packets. Each packet has a header followed in time by data. The header and data are sent as a packet, and the timing for the data in the packet is keyed from the header. The data may contain information such as digitized voice, signalling, adaptive power control (APC), cyclic-redundancy-check (CRC) code, etc.
The header, or preamble, is generated from spread-spectrum processing a header-symbol-sequence signal with a chip-sequence signal. The data part of the packet is generated from spread-spectrum processing a data-symbol-sequence signal with the chip-sequence signal. The chip-sequence signal for spread-spectrum processing the header-symbol-sequence signal and the data-symbol-sequence signal are preferably, but do not have to be, the same.
The spread-spectrum-matched filter, having a filter length of two halves, includes a first plurality of shift registers, a second plurality of shift registers, a third plurality of shift registers, a control processor, a multiplexer, a plurality of data-shift registers, a first plurality of exclusive-OR (XOR) gates, an adder tree, a plurality of memories, a second plurality of exclusive-OR XOR gates and an adder. The first plurality of shift registers stores a reference-chip-sequence signal and the optional second plurality of shift registers stores an additional set of reference-chip-sequence signal for programming the matched filter. Additional plurality of shift registers can be used to store more additional sets of reference-chip-sequence signal. The processor generates a clock signal. In response to the clock signal, the multiplexer outputs the corresponding set of chip-sequence signal during a first portion of the clock cycle, and then a corresponding set of chip-sequence signal during a second portion of the clock cycle.
The plurality of data-shift registers shifts input data samples of the received-spread-spectrum signal at the clock rate. During each clock cycle, the XOR gates multiply, correspondingly, the set of chip-sequence signal by the plurality of input data samples. This multiplication generates a first or second plurality of product-output signals.
During the first portion of the clock cycle, the adder tree sums the first plurality of product-output signals to generate a first sum. The first sum is stored in the memory. During the second portion of the clock cycle, the adder tree sums the second plurality of product-output signals to generate a second sum. The second plurality of exclusive OR (XOR) gates multiply the bit-sequence signal from the third plurality of shift registers by the first sum from the memory and by the second sum from the adder tree. The adder ads product sum from the second plurality of exclusive OR (XOR) gates.
Additional objects and advantages of the invention are set forth in part in the description which follows, and in part are obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention also may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.